This invention relates in general to power generation circuits for integrated circuits ("ICs") and in particular, to power generation circuits for ICs having flash electrically erasable and programmable read-only-memory ("flash EEPROM") cells.
ICs having flash EEPROM cells require a high voltage Vpp for programming and erasing the flash EEPROM cells in addition to a standard logic level voltage Vdd for reading the flash EEPROM cells. Accordingly, conventional systems employing such ICs (hereinafter referred to as "flash EEPROM chips") include in addition to a power supply providing the standard logic level voltage Vdd (e.g., 5.0 volts), either a second power supply providing the high voltage Vpp (e.g., 12.0 volts), or a DC--DC converter generating the high voltage Vpp from the standard logic level voltage Vdd.
FIGS. 1A-1B illustrate one example of a system employing flash EEPROM chips. In FIG. 1A, a flash EEPROM system 20 is illustrated wherein the flash EEPROM system 20 serves as a mass storage medium for a host computer 10 by emulating a hard disk system. The host computer 10 interfaces with the flash EEPROM system 20 by communicating conventional hard disk drive read and write commands through system bus 15 to a controller 40 in the flash EEPROM system 20. The controller 40 interprets the disk drive commands from the host computer 10, and translates them into corresponding read and write operations for a flash EEPROM module 30 in the flash EEPROM system 20, in a manner transparent to the host computer 10. Additional details of the operation of such a flash EEPROM system are described, for example, in U.S. patent application Ser. No. 07/736,733, filed Jul. 26, 1991, entitled "Solid-State Memory System Including Plural Memory Module Mounts and Serial Connections," and naming Robert D. Norman, Karl M. J. Lofgren, Jeffrey D. Stal, Anil Gupta, and Sanjay Mehrotra as inventors, which is incorporated herein by this reference.
In FIG. 1B, the flash EEPROM module 30 is further detailed as containing a plurality of flash EEPROM chips, 31-1 to 31-n, wherein each flash EEPROM chip, e.g., 31-1, is further detailed as including a plurality of flash EEPROM cells 33 and memory circuitry 34 for accessing selected ones of the flash EEPROM cells 33. Although not shown, the flash EEPROM cells 33 can be further organized in a matrix array and selectively accessed through a plurality of word lines connected to their respective control gates and a plurality of bit lines connected to their respective drains such as, for example, the flash EEPROM cell 33-1 of FIG. 3A.
In systems where the host computer 10 only provides a logic level voltage Vdd to the flash EEPROM system 20, such as, for example, in a personal computer system, the high voltage Vpp required for programming and erasing the flash EEPROM cells in the flash EEPROM system 20 is generated within the flash EEPROM system 20 itself. Such generation of the high voltage Vpp may be accomplished, for example, by including in the flash EEPROM system 20 a charge pump circuit or DC--DC converter device which generates the high voltage Vpp from the logic level voltage Vdd provided by the host computer 10.
FIGS. 2A-2C illustrate, as examples, three configurations for such an flash EEPROM system 20. In each of the configurations, at least one DC--DC converter is included within the flash EEPROM system 20 for generating the high voltage Vpp from the logic level voltage Vdd provided by the host computer 10. In FIG. 2A, the DC--DC converter device 46 is included in the controller 40; in FIG. 2B, the DC--DC converter device 46' is included in the flash EEPROM module 30; and FIG. 2C, DC--DC converter devices 46-1" to 46-n" are each respectively included in a corresponding one of the flash EEPROM chips 31-1 to 31-n of the flash EEPROM module 30.
In flash EEPROM systems where the controller 40 and the flash EEPROM module 30 are combined on a single printed circuit board, such as, for example, in a memory card adapted to be inserted into a slot provided in a personal computer, FIGS. 2A and 2B are substantially equivalent configurations. Such a configuration is described, for example, in U.S. Pat. No. 5,267,218 entitled "Non-volatile Memory Card with a Single Power Supply Input," and issued to Elbert, which is incorporated herein by this reference.
One problem with such a configuration as described in U.S. Pat. No. 5,267,218 is that the DC--DC converter device 46 is typically a separate component such as an LT1109-12 DC--DC converter manufactured by Linear Technology Corp. of Milpitas, Calif. As a consequence, the cost of this separate component must be added to the component costs of the processor 43 and flash EEPROM chips 31-1 to 31-n, thus increasing the component cost for the flash EEPROM system. Also, additional board space is required on the printed circuit board to accommodate such a separate component, thus increasing the board cost for the flash EEPROM system. Further, failure of this separate component results in failure of the entire flash EEPROM system, thus reducing the reliability of the flash EEPROM system. Such a problem is similarly experienced in configurations where the controller 40 and the flash EEPROM module 30 are on separate printed circuit boards.
In FIG. 2C, each of the flash EEPROM chips 31-1' to 31-n' includes a respective one of the DC--DC converters 46-1" to 46-n". By including a DC--DC converter on each of the flash EEPROM chips 31-1' to 31-n', the additional component cost of a separate DC--DC converter component is avoided, the additional board space required for the separate DC--DC converter component is avoided, and the reliability of the flash EEPROM system is enhanced through such redundancy. However, a major problem with including a DC--DC converter on each of the flash EEPROM chips 31-1' to 31-n' is that this approach increases the die size of the flash EEPROM chips and as a result, the costs of the flash EEPROM chips increases accordingly. In particular, where each of the DC--DC converters 46-1" to 46-n" is formed of a charge pump including a plurality of charge storage devices such as capacitors, the die area required for the charge storage devices may be considerable relative to that required for the flash EEPROM cells and memory circuitry on the flash EEPROM chip.
In certain flash EEPROM systems, a number of voltages V1 to Vk in lieu of or besides the high voltage Vpp may be required for properly operating the flash EEPROM cells of the flash EEPROM chips 31-1 to 31-n and 31-1' to 31-n'. Generally, these voltages V1 to Vk may be generated from the high voltage Vpp and/or logic level voltage Vdd by either on-chip circuitry such as circuits 32-1 to 32-n and 32-1' to 32-n' (FIGS. 2A-2C) respectively residing on flash EEPROM chips 31-1 to 31-n and 31-1' to 31-n', or by off-chip circuitry (not shown) residing, for example, on a printed circuit board of the flash EEPROM module 30, 30' or 30" (FIGS. 2A-2C, respectively). Additional details of certain flash EEPROM cells and their operational characteristics for one such flash EEPROM system are described, for example, in U.S. Pat. No. 5,198,380 entitled "Method of Highly Compact EPROM and Flash EEPROM Devices," and issued to Harari, which is incorporated herein by this reference.
In particular, FIGS. 3A and 3B illustrate one example of such voltages V1 to Vk required to operate one flash EEPROM cell 33-1 (e.g., FIG. 3A) of a plurality of flash EEPROM cells 33. To selectively program the flash EEPROM cell 33-1, its source "S" may be connected to ground "GND" (e.g., 0 volts), its drain "D" connected through bit line "BL" to 8.0 volts, its control gate "CG" connected through word line "WL" to 11.0 volts, and its erase gate "EG" connected to 2.0 volts. To read the flash EEPROM cell 33-1, its source "S" may be connected to ground "GND", its drain "D" connected through bit line "BL" to 1.0 volts, its control gate "CG" connected through word line "WL" to 5.0 volts, and its erase gate "EG" connected to 2.0 volts. To erase the flash EEPROM cell 33-1, its source "S", drain "D" and control "CG" gates may be connected to ground "GND", and its erase gate "EG" connected to 20.0 volts. Thus, in this simple example, to program, read, and erase the flash EEPROM cell 33-1, voltages of 20.0, 11.0, 8.0, 5.0, 2.0, 1.0 and ground (e.g., 0 volts) are required. In a more complicated example, additional voltages may also be required to verify the programming or erasing of the flash EEPROM cell 33-1.
Although described as fixed values in the above example, in practice, the optimal values for such operating voltages V1 to Vk may vary between different flash EEPROM chips initially (i.e., for flash EEPROM chips which have never been programmed and/or erased before), as well as for a given flash EEPROM chip over its operational life (i.e., for an flash EEPROM chip having increasing numbers of programming and erasing cycles). One reason for the optimal values of such programming, reading, and erasing voltages V1 to Vk to be different initially is that the optimal values for such voltages V1 to Vk are at least partially determined by the flash EEPROM chip's manufacturing process. Thus, flash EEPROM chips originating from different flash EEPROM manufacturers may have different optimal values and as a consequence, flash EEPROM systems employing flash EEPROM chips from different flash EEPROM manufacturers may have flash EEPROM chips having different optimal values initially. Although, this problem may be solved by including only flash EEPROM chips from one manufacturer in a flash EEPROM system, such a solution may often times be commercially impractical.
One reason for such optimal values to vary for a given flash EEPROM chip over the operational life of the flash EEPROM chip is that the optimal values for such voltages V1 to Vk for each flash EEPROM cell of the flash EEPROM chip are at least partially determined by the number of times that that flash EEPROM cell has been programmed and erased over its operational life. For example, as charge accumulates in an isolation region between a floating gate and erase gate of a flash EEPROM cell through repeated programming and erasures of the cell, it becomes increasingly difficult to erase the cell and consequently, higher and higher erase voltages may need to be applied to the erase gate to completely erase the cell within a reasonable period of time.
Conventional power generation circuits, such as those depicted in FIGS. 2A-2C, for flash EEPROM chips, however, are not adapted to providing such optimal programming, reading, and erasing voltages over the lifetime of their respective flash EEPROM chips. Generally, the voltages that they provide are fixed at the time of manufacture. Consequently, the voltages are set at a fixed level which may exceed the optimal programming, reading, and erasing voltages for each flash EEPROM cell early in the cell's lifetime, thus overstressing and reducing the life of the cell, and may fall short of the optimal programming, reading, and erasing voltages for each cell as the cell matures, thus resulting in increasing numbers of programming and erasure failures.